The increase in computing speeds of modern computing systems has created a demand for developing high speed memory devices. A high-speed synchronous system generally requires a tightly controlled dock timing allowance for a high performance operation. With source-synchronous interfaces such as, for example, a double data rate synchronous dynamic random access memory (DDR SDRAM) and a single data rate (SDR) SDRAM interfaces, data and dock transport from a transmitter to a receiver and a receiver interface employs the dock to latch an accompanying data. The device that transmits data also generates a data strobe signal that travels toward the receiving device along with the data signals. A source-synchronous SDR interface outputs data from the transmitter on one edge of the clock, typically the rising edge. The time required to transmit one bit, known as the unit interval (UI) is equal to the period of the dock. A DDR interface outputs data from the transmitter on both edges of the transmit clock (or strobe).
Conventional source synchronous memory interfaces such as, for example DDR/DDR2/DDR3 SDRAM and high speed NAND flash interface, requires a double rate (2×) clock at a physical layer to multiplex data from a memory controller single rate (1×) clock domain to DDR data, DQ, which transitions every double rate clock cycle. Additionally, a quarter cycle delay shifting of the read output data queue strobe (DOS) coming from the memory device is required to robustly sample the read output data queue (DQ) within a physical layer (PHY). Furthermore, skew must be tightly balanced across the DQ bits and between the DQS and DQ so as to maintain a good data eye at the memory interface for correct sampling the DQ by DOs within the memory device. Hence, a falling edge of a continuous dual rate (2×) clock with good duty cycle can be employed to launch the DQ bits at the same time, while the successive rising edge can launch the DQS.
The problem associated with prior art approaches is that the 2× clock toggles unnecessarily during an idle period and wastes power. Additionally, the source synchronous NAND flash (ONFI2.0) requires that the phase of the DQ relative to the DQS be switched dynamically between 90 and 180 degrees. A continuous 2× clock does not support phase switching when sampling from a continuous 1× clock. Also, it is difficult to satisfy both setup and hold requirements across process corners and OCV for high speed sampling from 1× clock to 2× clock. The setup time for the DQ path is only ¼ of the 1× period (90 degrees) and increasing the insertion delay on the 2× clock to increase setup reduces hold time on the DQS path. DQ and DQS paths require different logic to implement phase offsets from a common 2× clock. Such an approach results in a non-modular design which risks greater OCV variation due to logic and placement differences. Additionally, high speed physical layer design can suffer cross-coupling where the 2× clock can act as an aggressor against the read DQS during reads. Furthermore, read sampling of the DQ in the physical layer is highly sensitive to noise and aggressor signals, and requires a dedicated layout to avoid such noise signals.
Based on the foregoing, it is believed that a need exists for an improved system and method for interfacing a memory controller and a source synchronous memory utilizing a generic low power strobe, as described in greater detail herein.